1. Field of the Invention
This invention is related to the field of computer systems and, more particularly, to verifying source synchronous links within computer systems.
2. Description of the Related Art
Integrated circuits (or “chips”) have included built-in self test (BIST) circuitry in order to ensure that the internal circuits of the chips are functioning properly. Generally, the BIST applies a series of test vectors to the inputs of the internal circuits and compares the outputs of the internal circuits to expected results. If the outputs differ from the expected results, then the BIST fails and the chip may include a faulty internal circuit. BIST may be run on the chip at the time of manufacture of the integrated circuit to screen out faulty parts before delivery to a customer, and may be run when the system including the chip is powered up (or at some other time as may be desired) to ensure that the chip is still functioning properly.
The interconnect between chips has typically been synchronous, and has typically not been tested using any type of BIST. In a synchronous interconnect, a single system clock is used by each of the chips connected to the synchronous interconnect to time the driving of signals on the interconnect and the sampling of signals from the interconnect. Each chip is designed to meet certain timing criteria with respect to the clock signal (e.g. setup and hold times), and these timing criteria may be tested for each chip when that chip is manufactured. However, once the chips are assembled into a system, the testing of the interconnect is typically limited to in-circuit testing (ICT) or boundary scan testing (e.g. the type of tests specified by IEEE 1149 and 1149.1). ICT and boundary scan testing is typically performed at low clock frequencies, generally significantly lower than the operating frequency of the interconnect (i.e. the frequency at which the interconnect operates when the system is running). Accordingly, ICT and/or boundary scan testing may detect faults such as broken connections in the interconnect but may be severely limited in detecting timing-related failures.
Testing the interconnect may be even more important in the source synchronous interconnects that are becoming more popular in systems. A source synchronous interconnect includes a separate clock line (or lines) for each source of data transfers and one or more data lines for each source of data transfers. The source transmits a clock signal on the clock line (or lines) and concurrently transmits data on the data lines. The data is synchronized to the clock signal. The clock signal is used by a receiver on the interconnect to sample the data on the corresponding data lines. Generally, the length of the clock line and the corresponding data lines is matched (within a permissible variation tolerance) and thus the clock and the data take approximately the same amount of time to traverse the lines. Accordingly, more than one data transfer may be outstanding on the lines at any given time. Interference between the data transfers may be a source of failure, as well as timing related failures (e.g. a data bit failing to meet setup or hold time requirements at the receiver as measured against the corresponding clock signal arriving at the receiver). Additionally, since interconnect delay may be less of a factor in source synchronous interconnects, source synchronous interconnects are often operated at even higher operating frequencies then synchronous interconnects. Furthermore, source synchronous interconnects are often operated at double data rate (transferring a data bit on a line on both the rising edge and the falling edge of the clock signal). Accordingly, the frequency of data transfers is still higher. The potential for timing-related failures is thus still further increased.